Refactored sequencer functionality leveraging Python language capabilities. Implements uvm_component with hierarchy, uvm_root singleton,run_test(), simplified ConfigDB, uvm_driver, etc Leverages logging, controlled using UVM hierarchyĪll uvm_void classes automatically registered Uvm_object does not capture transaction timing information The following IEEE 1800.2 sections have been implemented: Section The code is based in the IEEE 1800.2 specification and most classes and methods have the specification references in the comments. The project refactors pieces of the UVM that were either overly complicated due to typing or legacy code. Pyuvm implements the most often-used parts of the UVM while taking advantage of the fact that Python does not have strict typing and does not require parameterized classes. pyuvm uses cocotb to interact with the simulator and schedule simulation events. Pyuvm is the Universal Verification Methodology implemented in Python instead of SystemVerilog.
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